重新讨论此问题：获取硬盘的工业序列号，CPU序列号，主板序列号(300分)

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guojun, 对此问题，您可以：
听听

,,

我也试了，用大富翁论谈上的方法取到的cpu的序列号同频率的相同，不同频率的不相同！！！

怪哉？

我在上面贴出的程序不能用Delphi编译，而应当用Turbo Pascal 7.0

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深有同感，虽然大富翁上一堆相关主题但都最终没有结果不了了之了，
现在我只想在PIII以上机器上取PIII序列号以保证唯一不知道各位可能指教!!!

给你一个vc的取得硬盘序列号的源程序算了。我是看不懂的。

lww: 我要，给我一份吧 ？

Please mail to : catyy1101@yeah.net

only you的方法当然不行因为那是在tp7.0+dos系统，DOS下是开放的可以随意读硬件端口，
windows没有0特权级是读不到的所以这些代码在win9x/nt下没有作用！

期待着真正的答案!

我用vc实现了PIII序列号的读取以前网上的cpuid只能读产品号同一批cpu相同，
是没有用的我这个可真的是序列号与intel的工具取得的一致，我想对大家会有用的!



======================================================
CString CGetcpuidCtrl::GetCpuId()
{
// TODO: Add your control notification handler code here
int EAX_,EDX_,ECX_;
CString rst="",rst2,rst3;

__asm{
MOV EAX,01H
CPUID
MOV EAX_,EAX
MOV EDX_,EDX
}
if (EDX_ & 0x00000100)
{
rst.Format("%8x",EAX_);
__asm{
MOV EAX,03H
CPUID
MOV EDX_,EDX
MOV ECX_,ECX
}
rst2.Format("%8x",EDX_);
rst3.Format("%8x",ECX_);
rst.Format("%s%s%s",rst,rst2,rst3);
}
else
{
rst="This Cpu Not Have PIII serialno";
}
return(rst);
}


to zhshfIII还是多数的,如要其它cpu,比较麻烦，但你可以看看!
======================================================

OPCODE CPUID - CPU Identification
CPU: Intel 486DX/SX/DX2 SL Enhanced and all later
Intel processors include ( IntelDX4, IntelSX2,
Pentium etc.), UMC microprocessors: U5S,U5SD,U5S-VL.
Cyrix M1, AMD K5, Intel P6, and AMD Ehnanced Am486 CPU,
such as A80486DX4-100SV8B.

Note: i.e. 1993+ years processors produced by Intel
Note: To know if your CPU support CPUID instruction
try to set ID flag ( bit 21 of EFLAGS ) to 1, and
if it sets this mean that CPUID support.(Soft).
Or If Your CPU is Intel Look for '&E' signature on
Top side of Chip.(Hard)

Type of Instruction: Operation

Instruction: CPUID

Description:

IF (EAX=0) THEN // All
{
EAX <- Maximum value of EAX to CALL CPUID instruction
1 for all processors (date 1 September 1994)
may be >1 in future microprocessors

; EBX,EDX and ECX contain a OEM name string
; for Intel this string is 'GenuineIntel'

EBX <- 756E6547H i.e. 'Genu'
EDX <- 49656E69H i.e. 'ineI'
ECX <- 6C65746EH i.e. 'ntel'

; for UMC this string is 'UMC UMC UMC '

EBX <- 20434D55H i.e. 'UMC '
EDX <- 20434D55H i.e. 'UMC '
ECX <- 20434D55H i.e. 'UMC '

; for Cyrix this string is 'CyrixInstead' (Cx6x86,Cx5x86 steps B+)
; for AMD this string is 'AuthenticAMD' (K6,K5,486 Enhanced CPUs)
; for last NexGen is 'NexGenDriven' (Nx5x86 latest models)
; for Centaur Technology is 'CentaurHauls' (IDT)
; for Rise Technology is 'RiseRiseRise'
}

ELSEIF (EAX=1) THEN // All
{
EAX[3:0] <- Stepping ID
EAX[7:4] <- Model
EAX[11:8] <- Family
; 3 - 386 family
; 4 - i486 family
; 5 - Pentium family
; 6 - Pentium Pro family
EAX[15:12] <- Reserved
; 0 - Original OEM processor
; 1 - OverDrive
; 2 - Dual Processor
Note: Pentium P54C have pin CPUTYPE which
define is this CPU First or Second e.t.c
in System.
So, if this chip set in "First" socket it
return for example 0425h, but THIS chip
return 2425h if we insert it in "Second"
socket.
Note: Refer to Appendix B for more information.


EAX[31:16] <- Reserved and set to 0s now
Note: This value in EAX[31:0] is upper 32-bit of 96-bit processor
serial number.

EDX <- Compability flags
; below all info if bit flag =1
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have Pentium Compatible MSRs
EDX[6] <- PAE: Physical Address Extension (Intel)
EDX[6] <- PTE: Support PTE (Cyrix)
When set in PTE TLB will not be flushed
when CR3 is written.
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- APIC: Local APIC on Chip (Intel)
PGE: Page Global Extension (K5)
EDX[10]<- reserved
EDX[11]<- SEP: Fast System Call feature (Pentium Pro)
EDX[12]<- MTRR: CPU support Memory Type Range Register (MTRR)
EDX[13]<- PGE: Page Global Feature support
EDX[14]<- MCA: Machine Check Architecture
EDX[15]<- CMOV: CPU support CMOV instruction
EDX[16]<- PAT: Page Attribute Table
EDX[17]<- PSE36: CPU support 4MB Pages for access memory higher
that 2GB.
EDX[18]<- SN: CPU Support Processor Serial Number
EDX[22..19] <- Reserved
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- FXSR: CPU Support Fast Save/Restore (IA MMX-2)
EDX[25] <- SIMD: Streaming SIMD Extension (IA MMX-2)
EDX[31:26] <- Reserved and set to 0s now

}

ELSEIF (EAX=2)
{
AL = 1 (Pentium Pro, Pentium II)
remainder of EAX and EBX,ECX,EDX contain bytes which
described cache architecture on this chip.
Description of this bytes is:
Value Description
00h None
01h Instruction TLB, 4K page, 4way, 64 entry
02h Instruction TLB, 4M page, 4way, 4 entry
03h Data TLB, 4K page, 4way, 64 entry
04h Data TLB, 4M page, 4way, 8 entry
06h Instruction Cache, 8K, 4 way, 32 byte per line
08h Instruction Cache, 16K, 4 way, 32 byte per line
0Ah Data cache, 8K, 2 way, 32 byte per line
0Ch Data cache, 16K, 4 way, 32 byte per line
40h No L2 cache
41h Unifed L2 cache, 32 byte per line, 4 way, 128KB
42h Unifed L2 cache, 32 byte per line, 4 way, 256KB
43h Unifed L2 cache, 32 byte per line, 4 way, 512KB
44h Unifed L2 cache, 32 byte per line, 4 way, 1MB
45h Unifed L2 cache, 32 byte per line, 4 way, 2MB
(Cyrix MediaGX MMX Enhanced)
70h TLB 32-bit entry, 4 way, 4K cache
80h L1 cache 4-way associative, 16byte/line
}
ELSEIF (EAX = 3) // Pentium III
{
EDX:ECX <- Lower 64-bit of 96-bit processor serial number.
}
ELSEIF (EAX = 80000000h) // (K5 not SSA/5),K6, Cyrix GXm
{
EBX,ECX,EDX <- Undefined
EAX <- Largest Extended function value recognized by CPUID.
(Note: Extended CPUID functions started with 80000000h)
(Example: For AMD 5k86 (K5) = 80000005h )
}

ELSEIF (EAX = 80000001h) // K5,K6,Cyrix GXm,IDT Winchip 2
{
EAX <- AMD Processor Signature
0000051Xh - for AMD 5k86 (K5 not SSA/5)
0000066Xh - for AMD 6k86 (K6)
EBX,ECX <- Undefined
EDX <- Extended Feature Flags
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have K5 Compatible MSRs
or Cyrix Compatible MSRs
EDX[6] <- PAE: Page Address Extensions
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- APIC: CPU have local APIC (must be enabled)
EDX[10] <- Reserved
EDX[11] <- SYSCALL and SYSRET Instructions (!)
EDX[12]<- MTRR: Memory Type Range Registers
EDX[13]<- Global Paging Extensions (PTE-PGE)
EDX[14]<- MCA: Machine Check Architecture
EDX[15]<- CMOV: CPU support CMOV instruction (!)
EDX[16]<- FCMOV: CPU support FP. FCMOV (!)
EDX[17]<- PSE: Page Size Extention
EDX[21..18] <- Reserved
EDX[22] <- MMXE: CPU Support Extended MMX instructions
(AMD Athlon)
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- (Cyrix) Cyrix Extended MMX support
EDX[24] <- (AMD) FXSAVE/FXRSTOR instruction support
EDX[29..24] <- Reserved
EDX[30] <- CPU support Extended 3DNow! Instructions
EDX[31] <- AMD 3DNow! support
Note: For AMD K5 = 000021BFh
For AMD K6 = 008005BFh
}

ELSEIF (EAX = 80000002h,80000003h,80000004h) // AMD K5,K6, Cyrix GXm
{ // IDT Winchip 2
EAX, EBX, ECX ,EDX = CPU Name

// Note: for AMD K5 (Don't forget x86 is BIG-Endian!!)
// CPUID(EAX) EAX EBX ECX EDX

// 80000002h 2D444D41 7428354B 5020296D 65636F72
// AMD- K5(r m) P roce

// 80000003h 726F7373 00000000 00000000 00000000
// ssor

// 80000004h 00000000 00000000 00000000 00000000
}


ELSEIF (EAX = 80000005h) // AMD K5,K6,Cyrix GXm
{ // L1 TLB and Cache information
EAX <- TLB Information (for 2M/4M pages):
see format of EBX.
EBX <- TLB Information (for 4K pages):
EBX[31..24] <- Data TLB: Associativity
(if Full assocuiativity = FFh)
see CPUID 80000006h for more datails
EBX[23..16] <- Data TLB: Number of Entryes
EBX[15..8] <- Instruction TLB: Associativity
(if Full assocuiativity = FFh)
EBX[7..0] <- Instruction TLB: Number of Entryes
ECX <- L1 Data Cache Information
ECX[31..24] <- Size in KB
ECX[23..16] <- Associativity (if full = FFh)
ECX[15..8] <- Lines per Tag
ECX[7..0] <- Line size in Bytes
EDX <- L1 Instruction Cache Information
ECX[31..24] <- Size in KB
ECX[23..16] <- Associativity (if full = FFh)
ECX[15..8] <- Lines per Tag
ECX[7..0] <- Line size in Bytes
// Note: after execution CPUID with EAX = 80000005h
// reg AMD K5 AMD K6
// EBX 04800000 02800140
// ECX 08040120 20020220
// EDX 10040120 20020220
}
ELSE THEN (EAX = 80000006h) // K6-III model-9, AMD Athlon
{ // L2 cache and TLB information
EAX = 2M/4M Pages and L2 TLB Info
bits description
31..28 Associativity (L2 Data TLB)
0000 L2 off
0001 Direct Mapped
0010 2-Way
0100 4-Way
0110 8-Way
1000 16-Way
1111 Full
27..16 Number of Entries (L2 Data TLB)
15..12 Associativity (L2 Instruction or Unifed TLB)
11..0 Number of entries (L2 Instruction or Unifed TLB)
EBX = 4K Pages and L2 TLB Info
bits description
31..28 Associativity (L2 Data TLB)
27..16 Number of Entries (L2 Data TLB)
15..12 Associativity (L2 Instruction or Unifed TLB)
11..0 Number of entries (L2 Instruction or Unifed TLB)
ECX = L2 Unifed Cache Info (K6-III: only this field)
bits description
31..16 Size (KB)
15..12 Associativity
11..8 Lines per tag
7..0 Line size (bytes)
EDX = reserved
}
ELSE THEN
{
EAX,EBX,ECX,EDX <- Undefined
}
END.

获取主板的工业序列号完全可以实现，注意是硬盘外壳上的序列号，不是格式化后的序列
号，C语言源程序如下（注：该程序由顶尖高手丁凯所写）：
#include <windows.h>
#include <stdio.h>

WORD pw[256];

static DWORD idt, int_idt;
static DWORD Base;
static WORD Entry;

#pragma warning (disable:4035)
static int inp(WORD rdx)
{
_asm xor eax, eax
_asm mov dx, rdx
_asm in al, dx
}

static WORD inpw(WORD rdx)
{
_asm xor eax, eax
_asm mov dx, rdx
_asm in ax, dx
}

static void outp(WORD rdx, int ral)
{
_asm mov dx, rdx
_asm mov eax, ral
_asm out dx, al
}

static int WaitIde()
{
int al;

while ((al=inp(0x1F7))>=0x80)
return al;
}

static void ReadIDE()
{
int al;
int i;

WaitIde();
outp(0x1F6,0xA0);
al = WaitIde();
if ((al&0x50)!=0x50) return;

outp(0x1F6,0xA0);
outp(0x1F7,0xEC);
al = WaitIde();
if ((al&0x58)!=0x58) return;

for (i=0;i<256;i++) {
pw = inpw(0x1F0);
}
}

static void __declspec( naked ) NowInRing0()
{
_asm {
push ebp
mov ebp,esp

call ReadIDE

cli
mov ebx, int_idt
mov ax, Entry
mov word ptr [ebx-4], ax
mov eax, Base
shr eax, 16
mov [ebx+2], ax
sti
leave
iretd
}
}

void GetIDEInfo()
{
DWORD dwExcept;

dwExcept = (DWORD)NowInRing0;

_asm {
mov eax, fs:[0]
push eax
sidt [esp-02h]
pop ebx
mov idt, ebx
add ebx, 0x1C
mov int_idt, ebx

mov eax, [ebx]
mov [Base], eax
mov ax, [ebx-4]
mov [Entry], ax

cli
mov esi, dwExcept
push esi
mov [ebx-4], si
shr esi, 16
mov [ebx+2], si
pop esi
sti

int 3
}
}

main()
{
char s[80];
register i,j;

GetIDEInfo();

for (i=0,j=0;i<10;i++) {
s[j++]=pw[10+i]>>8;
s[j++]=pw[10+i]&0xFF;
}
s[j] = 0;

printf("Serial=%s/n", s);

return 0;
}

*_*............@@

; 有关讨论硬件序列号的问题都是为了限制软件在不周的机子上安装,除
了通过硬件序列号的方法外,还有其它方法可行吗?这么多的delphi的高手难
道真束手无策吗?讨论了这么多期的问题,如果没有结果,能否大家来探讨一
个其它序列号生成密方法.我是十分佩服务unix的网上注册.不知大家有何实
现高见.

; 有关讨论硬件序列号的问题都是为了限制软件在不周的机子上安装,除
了通过硬件序列号的方法外,还有其它方法可行吗?这么多的delphi的高手难
道真束手无策吗?讨论了这么多期的问题,如果没有结果,能否大家来探讨一
个其它序列号生成密方法.我是十分佩服务unix的网上注册.不知大家有何实
现高见.

; 有关讨论硬件序列号的问题都是为了限制软件在不周的机子上安装,除
了通过硬件序列号的方法外,还有其它方法可行吗?这么多的delphi的高手难
道真束手无策吗?讨论了这么多期的问题,如果没有结果,能否大家来探讨一
个其它序列号生成密方法.我是十分佩服务unix的网上注册.不知大家有何实
现高见.

; 有关讨论硬件序列号的问题都是为了限制软件在不周的机子上安装,除
了通过硬件序列号的方法外,还有其它方法可行吗?这么多的delphi的高手难
道真束手无策吗?讨论了这么多期的问题,如果没有结果,能否大家来探讨一
个其它序列号生成密方法.我是十分佩服务unix的网上注册.不知大家有何实
现高见.

不好意思,网路问题,多传了!

zhshf 你好，如问题解决请mail给我你的答案。谢谢！！！
mchsoft@163.net